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Memory architecture
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#	Item
791	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.edu Add to Reading List Source URL: www-hydra.stanford.edu Language: English* - Date: 1999-11-05 21:09:40 Computer architecture CPU cache Cache Central processing unit Multi-core processor Parallel computing Direct memory access Harvard architecture Computer hardware Computing Computer memory
792	TWENTY-FIRST CENTURY HOTEL SYSTEMSTM INN SYSTEM FRONT OFFICE SOFTWARE SAMPLE REPORTS Add to Reading List Source URL: www.21stcenturycompany.com Language: English - Date: 2009-01-01 18:45:14 Compiler construction Procedural programming languages Computer memory Computer architecture Memory ordering Programming language design Chunking Memory barrier Compiler Computing Software engineering Programming language theory
793	Microsoft PowerPoint - BulkCompiler.MICRO09.FINAL [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 17:08:01 Compiler construction Procedural programming languages Computer memory Computer architecture Memory ordering Programming language design Chunking Memory barrier Compiler Computing Software engineering Programming language theory
794	INSTITUTE OF PHYSICS PUBLISHING NANOTECHNOLOGY Nanotechnology[removed]–230 Add to Reading List Source URL: www.cellmatrix.com Language: English - Date: 2002-03-16 03:24:12 Integrated circuits Computer memory Central processing unit Cell Field-programmable gate array Arithmetic logic unit Computer Digital signal processor Shift register Electronic engineering Electronics Computer architecture
795	FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes Rishi Agarwal and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:23:57 Parallel computing Lock Compiler optimization C dynamic memory allocation Memory barrier Hazard Critical section Linearizability Concurrency control Computing Computer architecture
796	M PIC16F84A Data Sheet 18-pin Enhanced FLASH/EEPROM 8-bit Microcontroller Add to Reading List Source URL: oap.sourceforge.net Language: English - Date: 2003-07-23 17:02:34 Electronics PIC microcontroller PIC16x84 EEPROM Interrupt Memory-mapped I/O PICAXE Intel MCS-51 Microcontrollers Computer architecture Computer hardware
797	DECchip[removed]and DECchip[removed]Core Logic Chipsets Data Sheet Order Number: EC–QAEMB–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:03:54 Instruction set architectures Computer memory Alpha 21064 Computer buses Minicomputers DEC Alpha Conventional PCI CPU cache VAX Computer hardware Computer architecture Computing
798	Software Logging under Speculative Parallelization ´ Garzar´an, Milos Prvulovicy , Jos´e Mar´ıa Llaber´ıaz , Mar´ıa Jesus ˜ V´ıctor Vinals, Lawrence Rauchwergerx , and Josep Torrellasy Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-09-30 19:59:18 Central processing unit Parallel computing Microprocessors Computer memory CPU cache Microarchitecture Cache Automatic parallelization Superscalar Computer hardware Computer architecture Computing
799	MUX Chip Specification 1. Introduction This document specifies the architecture of the MUX gate array for the Fast Forward project. This array connects the R4000 processor to the the memory system and the GIO64 Bus. Each Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:59 R4000 Central processing unit Multiplexer Electronics Intel MCS-51 GIO Universal asynchronous receiver/transmitter Q-Bus Computer buses Computer hardware Electronic engineering
800	SWICH: A PROTOTYPE FOR EFFICIENT CACHE-LEVEL CHECKPOINTING AND ROLLBACK EXISTING CACHE-LEVEL CHECKPOINTING SCHEMES DO NOT CONTINUOUSLY SUPPORT A LARGE ROLLBACK WINDOW. IMMEDIATELY AFTER A CHECKPOINT, THE NUMBER OF INSTRU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-05-03 11:36:50 Computer memory Computer engineering Cache Application checkpointing CPU cache Microarchitecture SPARC64 Memory hierarchy Runahead Computer hardware Computer architecture Central processing unit

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